In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits, such as application specific integrated circuit (ASIC) chips, random access memory (RAM) chips, microprocessor (uP) chips, and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices. A SOC device integrates into a single chip all (or nearly all) of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, and the like). SOC devices greatly reduce the size, cost, and power consumption of the system.
Reductions in power consumption are particularly important in SOC designs. SOC devices are frequently used in portable devices that operate on battery power. Since maximizing battery life is a critical objective in a portable device, it is essential to minimize the power consumption of SOC devices that may be used in the portable device. Furthermore, even if an SOC device is not used in a portable device, minimizing power consumption is still an important objective. The increased use of a wide variety of electronic products by consumers and businesses has caused corresponding increases in the electrical utility bills of homeowners and business operators. The increased use of electronic products also is a major contributor to the increased electrical demand that has caused highly publicized power shortages in California.
To minimize power consumption in electronic devices, particularly SOC devices, many manufacturers have reduced the voltage levels at which electronic components operate. Low power integrated circuit (IC) technology operating at +3.3 volts replaced IC technology operating at +5.0 volts. The +3.3 volt IC technology was, in turn, replaced by +1.6 volt IC technology in many applications, particularly microprocessor and memory applications.
However, as the operating voltage of an integrated circuit is reduced, the noise margins of the integrated circuit are also reduced. Thus, an integrated circuit operating at +1.6 volts has smaller noise margins than a circuit operating at +3.3 volts. During higher speed operation, the fast switching times of the N-type and P-type transistors that drive signal lines in an integrated circuit cause ground bounce and power supply noise that reduce the available noise margins. Furthermore, the ground bounce and power supply noise caused by the fast switching of transistors often does not go away during lower speed operation. At lower speeds, the line drivers still switch rapidly from Logic 1 to Logic 0 and vice versa, only the periods between transitions are extended.
Therefore, there is a need in the art for system-on-a-chip (SOC) devices and other large scale integrated circuit devices that are capable of operating with low noise margins. In particular, there is a need in the art for SOC devices and other large scale integrated circuit devices that have reduced ground bounce and power supply noise caused by the high-speed switching of logic gates. More particularly, there is a need for SOC devices and other large scale integrated circuit devices that incorporate line drivers that have reduced ground bounce and power supply noise caused by the high-speed switching of P-type and N-type transistors.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, a reduced noise line driver for driving a signal line in an integrated circuit. According to an advantageous embodiment of the present invention, the reduced-noise line driver comprises: 1) an N-type transistor having a source coupled to ground and a drain coupled to the signal line; 2) a P-type transistor having a source coupled to a power supply rail and a drain coupled to the signal line; 3) a first controller having an input for receiving an incoming signal and an output coupled to a gate of the N-type transistor; and 4) a second controller having an input for receiving the incoming signal and an output coupled to a gate of the P-type transistor, wherein the first controller and the second controller selectively switch the N-type transistor and the P-type transistor ON and OFF such that the N-type transistor and the P-type transistor are never ON simultaneously.
According to one embodiment of the present invention, the first controller comprises a comparator capable of determining when the incoming signal is a Logic 1 and, in response to the determination, turning ON the N-type transistor.
According to another embodiment of the present invention, the first controller further comprises circuitry for turning ON the N-type transistor using a ramp function.
According to still another embodiment of the present invention, the first controller further comprises delay circuitry for delaying the ramp function by a predetermined delay period after the comparator has determined the incoming signal is a Logic 1.
According to yet another embodiment of the present invention, the first controller further comprises delay circuitry for delaying the ramp function by a predetermined delay period after the incoming signal has switched from a Logic 0 to a Logic 1.
According to a further embodiment of the present invention, the second controller comprises a comparator capable of determining when the incoming signal is a Logic 0 and, in response to the determination, turning ON the P-type transistor.
According to a still further embodiment of the present invention, the second controller further comprises circuitry for turning ON the P-type transistor using a ramp function.
According to a yet further embodiment of the present invention, the second controller further comprises delay circuitry for delaying the ramp function by a predetermined delay period after the comparator has determined the incoming signal is a Logic 0.
According to still another embodiment of the present invention, the second controller further comprises delay circuitry for delaying the ramp function by a predetermined delay period after the incoming signal has switched from a Logic 1 to a Logic 0.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.